1. Field of the Invention
The present invention relates to programming non-volatile memory.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
When programming an EEPROM or flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in the programmed state. More information about programming can be found in U.S. patent application Ser. No. 10/379,608, titled “Self Boosting Technique,” filed on Mar. 5, 2003; and in U.S. patent application Ser. No. 10/629,068, titled “Detecting Over Programmed Memory,” filed on Jul. 29, 2003, both applications are incorporated herein by reference in their entirety.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states (an erased state and a programmed state). For example, FIG. 1 shows a graph depicting two threshold voltage distributions. The x axis plots threshold voltage and the y axis plots the number of memory cells. Threshold voltage distribution 2 is less than zero volts. In one embodiment, threshold voltage distribution 2 corresponds to erased memory cells that store data “1.” Threshold voltage distribution 4 is greater than zero volts. In one embodiment, threshold voltage distribution 4 corresponds to programmed memory cells that store data “0.”
A multi-state flash memory cell is implemented by identifying multiple, distinct allowed threshold voltage ranges separated by forbidden voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits. FIG. 2 illustrates threshold voltage distributions for memory cells storing two bits of data (e.g., four data states). In one embodiment, threshold voltage distribution 2 represents memory cells that are in the erased state (e.g., storing “11”), having negative threshold voltage levels. Threshold voltage distribution 10 represents memory cells that store data “10,” having positive threshold voltage levels. Threshold voltage distribution 12 represents memory cells storing data “00.” Threshold voltage distribution 14 represents memory cells that are storing “01.” In other embodiments, each of the distributions can correspond to different data states than described above. In some implementations (as exemplified above), these data values (e.g. logical states) are assigned to the threshold ranges using a gray code assignment so that if the threshold voltage of a floating gate erroneously shifts to its neighboring physical state, only one logical bit will be affected. The specific relationship between the data programmed into the memory cell and the threshold voltage ranges of the cell depends upon the data encoding scheme adopted for the memory cells. For example, U.S. Pat. No. 6,222,762 and U.S. patent application Ser. No. 10/461,244, “Tracking Cells For A Memory System,” filed on Jun. 13, 2003, both of which are incorporated herein by reference in their entirety, describe various data encoding schemes for multi-state flash memory cells. Additionally, the present is applicable to memory cells that store more than two bits of data.
Threshold voltage distributions 2 and 4 show the erased and programmed voltage-distributions when no verify operations are used. These distributions can be obtained by programming or erasing the memory cells with one single programming or erase pulse. Depending on the memory array size and the variations in the production process, the threshold voltage distribution 4 has a certain width, known as the natural Vt width.
As can be seen from FIG. 2, distributions 10, 12, and 14 (corresponding to programming a multi-state device) need to be much narrower than the natural Vt width of distribution 4. To achieve such narrower threshold voltage distributions a process that uses multiple programming pulses and verify operations, such as that described by FIGS. 3A, 3B, and 3C, can be used.
FIG. 3A depicts a programming voltage signal Vpgm that is applied to the control gate as a series of pulses. The magnitude of the pulses is increased with each successive pulse by a pre-determined step size (e.g., 0.2 v–0.4 v), depicted in FIG. 3A as ΔVpgm. In the periods between the pulses, verify operations are carried out. As the number of programmable states increase, the number of verify operations increases and more time is needed. One means for reducing the time-burden is a more efficient verified process, such as the process that is disclosed in U.S. patent application Ser. No. 10/314,055 “Smart Verify For Multi-State Memories,” filed Dec. 5, 2002, incorporated herein by reference in its entirety. In reality, the pulses of FIG. 3A are separated from each other by a time period for verification. However, to make FIG. 3 more readable, the time period for verification is omitted from the drawing.
FIG. 3B depicts the voltage signal applied to a bit line for the associated memory cell being programmed. FIG. 3C depicts the threshold voltage of the memory cell being programmed. Note that the graph in FIG. 3C is smoothed out to make it easier to read. After each programming pulse, a verify operation is carried out (not shown.) During the verify operation, the threshold voltage of the memory cell to be programmed is checked. If the memory cell of the threshold voltage is larger than the target value (e.g., Vverify), then programming for that memory cell is inhibited in the next cycle by raising the bit line voltage from 0 v to Vinhibit (e.g., at time t4).
As with other electronic devices, there is a consumer demand for memory devices to program as fast as possible. For example, the user of a digital camera that stores images on a flash memory card does not want to wait between pictures for an unnecessary long period of time. In addition to programming with reasonable speed, to achieve proper data storage for a multi-state memory cell, the multiple ranges of threshold voltages of the multi-state memory cells should be separated from each other by sufficient margin so that the level of the memory cell can be programmed and read in an unambiguous manner. Additionally, a tight threshold voltage distribution is recommended. To achieve a tight threshold voltage distribution, small program steps have typically been used, thereby, programming the threshold voltage of the cells more slowly. The tighter the desired threshold voltage distribution the smaller the steps and the slower the programming process.
One solution for achieving tight threshold voltage distributions, without unreasonably slowing down the programming process, includes using a two-phase programming process. The first phase, a coarse programming phase, includes an attempt to raise a threshold voltage in a faster manner and paying less attention to achieving a tight threshold voltage distribution. The second phase, a fine programming phase, attempts to raise the threshold voltage in a slower manner in order to reach the target threshold voltage, while also achieving a tighter threshold voltage distribution. One example of a coarse/fine programming methodology can be found in U.S. Pat. No. 6,643,188, incorporated herein by reference in its entirety.
FIGS. 4 and 5 provide more detail of one example of a coarse/fine programming methodology. FIGS. 4A and 5A depict the programming pulses Vpgm applied to the control gate. FIGS. 4B and 5B depict the bit line voltages for the memory cells being programmed. FIGS. 4C and 5C depict the threshold voltage of the memory cells being programmed. This example of FIGS. 4 and 5 uses two verify levels, indicated in the Figures as Vver1 and Vver2. The final target level is Vver1. When a threshold voltage of the memory cell has reached Vver1, the memory cell will be inhibited from further programming by applying an inhibit voltage to the bit line corresponding to that memory cell. For example, the bit line voltage can be raised to Vinhibit (See FIG. 4B and FIG. 5B). However, when a memory cell has reached a threshold voltage close to (but lower than) the target value Vver1, the threshold voltage shift to the memory cell during subsequent programming pulses is slowed down by applying a certain bias voltage to the bit line, typically in the order of 0.3 v to 0.8 v. Because the rate of threshold voltage shift is reduced during the next few programming pulses, the final threshold voltage distribution can be narrower than with the methods depicted in FIG. 3. To implement this method, a second verify level that is lower than that of Vver1 is used. This second verify level is depicted in FIGS. 4 and 5 as Vver2. When the threshold voltage of the memory cell is larger than Vver2, but still lower than Vver1, the threshold voltage shift to the memory cell will be reduced for subsequent programming pulses by applying a bit line bias Vs (FIG. 5B). Note that in this case, two verify operations are required for each state. One verify operation at the corresponding Vver1 for each state, and one verify operation at the corresponding Vver2 for each state. This may increase the total time needed to program the memory cells. However, a large ΔVpgm step size can be used to speed up the process.
FIGS. 4A, 4B, and 4C show the behavior of a memory cell whose threshold voltage moves past Vver2 and Vver1 in one programming pulse. For example, the threshold voltage is depicted in FIG. 4C to pass Vver2 and Vver1 in between t2 and t3. Thus, prior to t3, the memory cell is in the coarse phase. After t3, the memory cell is in the inhibit mode.
FIGS. 5A, 5B, and 5C depict a memory cell that enters both the coarse and fine programming phases. The threshold voltage of the memory cell crosses Vver2 in between time t2 and time t3. Prior to t3, the memory cell is in the coarse phase. After t3, the bit line voltage is raised to Vs; therefore, the memory cell is in the fine phase. In between t3 and t4, the threshold voltage of the memory cell crosses Vver1; therefore, the memory cell is inhibited from further programming by raising the bit line voltage to Vinhibit.
One problem experienced by non-volatile memory, particularly multi-state memory, is that over-programming can occur. During the programming process, the memory cells are programmed to a certain target state defined by the threshold voltage range for that particular set of data. When a memory cell is programmed to a certain threshold voltage range, the threshold voltage of that cell should not exceed the maximum allowed threshold voltage for that range. For example, looking at FIG. 2, if the memory cell is to be programmed to target state 10, the memory cell's threshold voltage should be raised to be higher than Vv1, however should stay below Vmax 1, the maximum allowable threshold voltage for distribution 10. When the threshold voltage of the memory cell exceeds the allowable range, there may be a failure when reading the data later on. This phenomenon is called over-programming. In some cases, error correction can be used to correct errors caused by over-programming. However, some over-programming cannot be rectified by error correction. Additionally, error correction can be very time consuming.
FIG. 6 depicts erased threshold voltage distribution 2 and programmed threshold voltage distribution 80. Threshold voltage distribution 80 includes a set of one or more memory cells that program faster than normal. These fast memory cells are candidates for being over-programmed. For example, after one program pulse, instead of obtaining threshold voltage distribution 4 of FIG. 1, the population of memory cells that includes one or more fast cells will result in threshold voltage distribution 80 of FIG. 6. Threshold voltage distribution 80 includes fast memory cells 82.
FIGS. 7A, 7B, and 7C further illustrate a problem with fast memory cells that can be over-programmed. FIG. 7A, depicts the threshold voltage distributions 2, 10, 12 and 14 for a two-bit multi-state memory cell. FIG. 7B shows natural erased threshold voltage distribution 2 and programmed threshold voltage distribution 84. In one embodiment, distribution 84 is associated with the population of memory cells intended to be programmed to distribution 10, after one programming pulse. As can be seen, the distribution is moved over towards what should be distribution 10. Distribution 84 includes a set of fast memory cells, some of which exceed the read verify point Vr1. As can be seen from FIG. 7A, the read verify point is the voltage level used to distinguish between threshold voltage distribution 10 and threshold voltage distribution 12. Therefore, after one programming pulse, some of the memory cells in threshold voltage distribution 84 already have an error because they have a threshold voltage distribution greater than Vr1. At the end of the programming process, those memory cells intended to be in threshold voltage distribution 10 will likely be in distribution 86, as depicted in FIG. 7C. The difference between threshold voltage distribution 86 and threshold voltage distribution 10 of FIG. 7A, is that threshold voltage distribution 86 includes a set of fast memory cels (the front-end tail of distribution 86) that have threshold voltage that exceeds Vr1. These fast bits with a threshold voltage greater than Vr1 can return an error when read.